The present application describes systems and techniques relating to semiconductor-based imaging devices, for example, reducing fixed pattern noise in single-chip active pixel sensors.
A traditional design for an image sensor on a semiconductor chip consists of an image sensor array, column circuitry that includes a gain stage, an analog-to-digital converter and digital control logic to generate control signals. Traditional image sensors can introduce fixed pattern noise, which is undesirable in high-quality imaging systems, such as camera systems designed to operate in low light levels. A typical approach to suppress such fixed pattern noise is to add calibration circuitry, which generally increases design complexity and power requirements.
The present application teaches an array-based analog data readout architecture with reduced power requirements and reduced fixed pattern noise. The array-based analog data readout architecture may perform a serial pipelined amplification outside of a parallel array sampling circuitry. Pipelining uses two separate clock signals to alternately reset and amplify array data stored in the parallel sampling circuitry. A pipelined analog-to-digital converter may be used to further reduce power requirements. The array-based analog data readout architecture may be used with active pixel sensors on integrated circuits in high-quality imaging systems.
One or more of the following advantages may be provided. The systems and techniques described may result in reduced fixed pattern noise in high-quality imaging systems, such as in camera systems designed to operate in low light levels. Low-power readout of analog data on an integrated circuit may result in reduced power dissipation and corresponding reduced dark current.
Additionally, the reduced complexity of parallel sampling circuitry may result in fewer layout limitations due to pixel pitch. The reduced complexity may also result in signal gain with reduced area and optimized performance, and higher yield during manufacturing of integrated circuits that use the systems and techniques described.
Details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims.